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1 features ? medium-voltage and standard-voltage operation ? 5.0 (v cc = 4.5v to 5.5v) ? 2.7 (v cc = 2.7v to 5.5v) user-selectable internal organization ? 1k: 128 x 8 or 64 x 16 ? 2k: 256 x 8 or 128 x 16 ? 4k: 512 x 8 or 256 x 16 three-wire serial interface 2 mhz clock rate (5v) self-timed write cycle (10 ms max) high reliability ? endurance: 1 million write cycles ? data retention: 100 years 8-lead pdip and 8-lead jedec soic packages description the at93c46/56/66 provides 1024/2048/4096 bits of serial electrically erasable pro- grammable read only memory (eeprom) organized as 64/128/256 words of 16 bits each, when the org pin is connected to vcc and 128/256/512 words of 8 bits each when it is tied to ground. the device is optimized for use in many automotive applica- tions where low power and low voltage operations are essential. the at93c46/56/66 is available in space-saving 8-lead pdip and 8-lead jedec soic packages. the at93c46/56/66 is enabled through the chip select pin (cs), and accessed via a 3-wire serial interface consisting of data input (di), data output (do), and shift clock (sk). upon receiving a read instruction at di, the address is decoded and the data is clocked out serially on the data output pin do. the write cycle is completely self- timed and no separate erase cycle is required before write. the write cycle is only enabled when it is in the erase/write enable state. when cs is brought ?high? follow- ing the initiation of a write cycle, the do pin outputs the ready/busy status. the at93c46/56/66 is available in 4.5v to 5.5v and 2.7v to 5.5v versions. table 1. pin configuration pin name function cs chip select sk serial data clock di serial data input do serial data output gnd ground vcc power supply org internal organization three-wire serial automotive eeproms 1k (128 x 8 or 64 x 16) 2k (256 x 8 or 128 x 16) 4k (512 x 8 or 256 x 16) at93c46 at93c56 (1) at93c66 (2) note: 1. this device is not recom- mended for new designs. please refer to at93c56a. 2. this device is not recom- mended for new designs. please refer to at93c66a. rev. 3264e?seepr?10/04 8-lead pdip 1 2 3 4 8 7 6 5 cs sk di do vcc dc org gnd 8-lead soic 1 2 3 4 8 7 6 5 cs sk di do vcc dc org gnd
2 at93c46/56/66 3264e?seepr?10/04 figure 1. block diagram note: when the org pin is connected to vcc, the ?x 16? organization is selected. when it is connected to ground, the ?x 8? organ iza- tion is selected. if the org pin is left unconnected and the application does not load the input beyond the capability of the internal 1 meg ohm pullup, then the ?x 16? organization is selected. for the at93c46, if ?x 16? organization is the mode of choice and pin 6 (org) is left unconnected, atmel recommends using the at93c46a device. for more details, see the at93c46a datasheet. absolute maximum ratings* operating temperature ......................................? 55 c to +125 c *notice: stresses beyond those listed under ?absolute maxi- mum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other condi- tions beyond those indicated in the operational sec- tions of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability storage temperature .........................................? 65 c to +150 c voltage on any pin with respect to ground ........................................ ? 1.0v to +7.0v maximum operating voltage .......................................... 6.25v dc output current........................................................ 5.0 ma
3 at93c46/56/66 3264e?seepr?10/04 note: 1. this parameter is characterized and is not 100% tested. note: 1. v il min and v ih max are reference only and are not tested. table 2. pin capacitance (1) applicable over recommended operating range from t a = 25 c, f = 1.0 mhz, v cc = +5.0v (unless otherwise noted). symbol test conditions max units conditions c out output capacitance (do) 5 pf v out = 0v c in input capacitance (cs, sk, di) 5 pf v in = 0v table 3. dc characteristics applicable over recommended operating range from: t a = ? 40 c to +125 c, v cc = +2.7v to +5.5v (unless otherwise noted). symbol parameter test condition min typ max unit v cc1 supply voltage 2.7 5.5 v v cc2 supply voltage 4.5 5.5 v i cc supply current v cc = 5.0v read at 1.0 mhz 0.5 2.0 ma write at 1.0 mhz 0.5 2.0 ma i sb1 standby current v cc = 2.7v cs = 0v 6.0 10.0 a i sb2 standby current v cc = 5.0v cs = 0v 17 30 a i il input leakage v in = 0v to v cc 0.1 1.0 a i ol output leakage v in = 0v to v cc 0.1 1.0 a v il1 (1) input low voltage 2.7v v cc 5.5v ? 0.6 v cc x 0.3 v ih1 (1) input high voltage v cc x 0.7 v cc + 1 v v ol1 output low voltage 2.7v v cc 5.5v i ol = 2.1 ma 0.4 v v oh1 output high voltage i oh = ? 0.4 ma 2.4 v
4 at93c46/56/66 3264e?seepr?10/04 note: 1. this parameter is characterized and is not 100% tested. table 4. ac characteristics applicable over recommended operating range from t a = ? 40c to + 125c, v cc = as specified, cl = 1 ttl gate and 100 pf (unless otherwise noted). symbol parameter test condition min typ max units f sk sk clock frequency 4.5v v cc 5.5v 2.7v v cc 5.5v 0 0 2 1 mhz t skh sk high time 4.5v v cc 5.5v 2.7v v cc 5.5v 250 250 ns t skl sk low time 4.5v v cc 5.5v 2.7v v cc 5.5v 250 250 ns t cs minimum cs low time 4.5v v cc 5.5v 2.7v v cc 5.5v 250 250 ns t css cs setup time relative to sk 4.5v v cc 5.5v 2.7v v cc 5.5v 50 50 ns t dis di setup time relative to sk 4.5v v cc 5.5v 2.7v v cc 5.5v 100 100 ns t csh cs hold time relative to sk 0 ns t dih di hold time relative to sk 4.5v v cc 5.5v 2.7v v cc 5.5v 100 100 ns t pd1 output delay to ?1? ac test 4.5v v cc 5.5v 2.7v v cc 5.5v 250 500 ns t pd0 output delay to ?0? ac test 4.5v v cc 5.5v 2.7v v cc 5.5v 250 500 ns t sv cs to status valid ac test 4.5v v cc 5.5v 2.7v v cc 5.5v 250 250 ns t df cs to do in high impedance ac test cs = v il 4.5v v cc 5.5v 2.7v v cc 5.5v 100 100 ns t wp write cycle time 2.7v v cc 5.5v 3 10 ms endurance (1) 5.0v, 25c 1m write cycles
5 at93c46/56/66 3264e?seepr?10/04 note: the xs in the address field represent don?t care values and must be clocked. note: 1. this device is not recommended for new designs. please refer to at93c56a. 2. this device is not recommended for new designs. please refer to at93c66a. 3. the xs in the address field represent don?t care values and must be clocked. table 5. instruction set for the at93c46 instruction sb op code address data comments x 8 x 16 x 8 x 16 read 1 10 a 6 - a 0 a 5 - a 0 reads data stored in memory, at specified address ewen 1 00 11xxxxx 11xxxx write enable must precede all programming modes erase 1 11 a 6 - a 0 a 5 - a 0 erase memory location a n - a 0 write 1 01 a 6 - a 0 a 5 - a 0 d 7 - d 0 d 15 - d 0 writes memory location a n - a 0 eral 1 00 10xxxxx 10xxxx erases all memory locations. valid only at v cc = 4.5v to 5.5v wral 1 00 01xxxxx 01xxxx d 7 - d 0 d 15 - d 0 writes all memory locations. valid only at v cc = 4.5v to 5.5v ewds 1 00 00xxxxx 00xxxx disables all programming instructions table 6. instruction set for the at93c56 (1) and at93c66 (2) instruction sb op code address data comments x 8 x 16 x 8 x 16 read 1 10 a 8 - a 0 a 7 - a 0 reads data stored in memory, at specified address ewen 1 00 11xxxxxxx 11xxxxxx write enable must precede all programming modes erase 1 11 a 8 - a 0 a 7 - a 0 erase memory location a n - a 0 write 1 01 a 8 - a 0 a 7 - a 0 d 7 - d 0 d 15 - d 0 writes memory location a n - a 0 eral 1 00 10xxxxxxx 10xxxxxx erases all memory locations. valid only at v cc = 4.5v to 5.5v wral 1 00 01xxxxxxx 01xxxxxx d 7 - d 0 d 15 - d 0 writes all memory locations. valid only at v cc = 5.0v 10% and disable register cleared ewds 1 00 00xxxxxxx 00xxxxxx disables all programming instructions
6 at93c46/56/66 3264e?seepr?10/04 functional description the at93c46/56/66 is accessed via a simple and versatile 3-wire serial communication interface. device operation is controlled by seven instructions issued by the host pro- cessor. a valid instruction starts with a rising edge of cs and consists of a start bit (logic ?1?) followed by the appropriate op code and the desired memory address location. read (read): the read (read) instruction contains the address code for the mem- ory location to be read. after the instruction and address are decoded, data from the selected memory location is available at the serial output pin do. output data changes are synchronized with the rising edges of serial clock sk. it should be noted that a dummy bit (logic ?0?) precedes the 8- or 16-bit data output string. erase/write (ewen): to assure data integrity, the part automatically goes into the erase/write disable (ewds) state when power is first applied. an erase/write enable (ewen) instruction must be executed first before any programming instructions can be carried out. please note that once in the ewen state, programming remains enabled until an ewds instruction is executed or v cc power is removed from the part. erase (erase): the erase (erase) instruction programs all bits in the specified memory location to the logical ?1? state. the self-timed erase cycle starts once the erase instruction and address are decoded. the do pin outputs the ready/busy sta- tus of the part if cs is brought high after being kept low for a minimum of 250 ns (t cs ). a logic ?1? at pin do indicates that the selected memory location has been erased, and the part is ready for another instruction. write (write): the write (write) instruction contains the 8 or 16 bits of data to be written into the specified memory location. the self-timed programming cycle, t wp , starts after the last bit of data is received at serial data input pin di. the do pin outputs the ready/busy status of the part if cs is brought high after being kept low for a minimum of 250 ns (t cs ). a logic ?0? at do indicates that programming is still in progress. a logic ?1? indicates that the memory location at the specified address has been written with the data pattern contained in the instruction and the part is ready for further instructions. a ready/busy status cannot be obtained if the cs is brought high after the end of the self- timed programming cycle, t wp . erase all (eral): the erase all (eral) instruction programs every bit in the mem- ory array to the logic ?1? state and is primarily used for testing purposes. the do pin outputs the ready/busy status of the part if cs is brought high after being kept low for a minimum of 250 ns (t cs ). the eral instruction is valid only at v cc = 5.0v 10%. write all (wral) : the write all (wral) instruction programs all memory locations with the data patterns specified in the instruction. the do pin outputs the ready/busy status of the part if cs is brought high after being kept low for a minimum of 250 ns (t cs ). the wral instruction is valid only at v cc = 5.0v 10%. erase/write disable (ewds): to protect against accidental data disturb, the erase/write disable (ewds) instruction disables all programming modes and should be executed after all programming operations. the operation of the read instruction is independent of both the ewen and ewds in structions and can be executed at any time.
7 at93c46/56/66 3264e?seepr?10/04 timing diagrams figure 2. synchronous data timing note: 1. this is the minimum sk period. notes: 1. this device is not recommended for new designs. please refer to at93c56a. 2. this device is not recommended for new designs. please refer to at93c66a. 3. a 8 is a don?t care value, but the extra clock is required. 4. a 7 is a don?t care value, but the extra clock is required. figure 3. read timing table 7. organization key for timing diagrams i/o at93c46 (1k) at93c56 (2k) (1) at93c66 (4k) (2) x 8 x 16 x 8 x 16 x 8 x 16 a n a 6 a 5 a 8 (3) a 7 (4) a 8 a 7 d n d 7 d 15 d 7 d 15 d 7 d 15 high impedance t cs
8 at93c46/56/66 3264e?seepr?10/04 figure 4. ewen timing figure 5. ewds timing figure 6. write timing figure 7. wral timing (1) note: 1. valid only at v cc = 4.5v to 5.5v. cs 11 ... 00 1 sk di t cs cs t cs sk di 1 0 000 ... sk cs t cs t wp 11 a n d n 0a0d0 ... ... di do high impedance busy ready cs sk di do high impedance busy ready 1 0 0 1 ... d n t cs t wp ... d0 0
9 at93c46/56/66 3264e?seepr?10/04 figure 8. erase timing figure 9. eral timing (1) note: 1. valid only at v cc = 4.5v to 5.5v. sk 1 1 ... 1 cs di a n t cs t sv t df t wp a n-1 a n-2 a0 check status standby ready busy do high impedance high impedance sk cs di 1 1 00 0 do high impedance high impedance ready busy check status standby t wp t cs t sv t df
10 at93c46/56/66 3264e?seepr?10/04 at93c46 ordering information ordering code package operation range at93c46-10pa-5.0c at93c46-10sa-5.0c 8p3 8s1 automotive ( ? 40 c to 125 c) at93c46-10pa-2.7c at93c46-10sa-2.7c 8p3 8s1 automotive ( ? 40 c to 125 c) package type 8p3 8-lead, 0.300" wide, plastic dual inline package (pdip) 8s1 8-lead, 0.150" wide, plastic gull wing small outline (jedec soic) options ? 5.0 standard operation (4.5v to 5.5v) ? 2.7 low voltage (2.7v to 5.5v)
11 at93c46/56/66 3264e?seepr?10/04 note: 1. this device is not recommended for new designs. please refer to at93c56a. at93c56 (1) ordering information ordering code package operation range at93c56-10pa-5.0c at93c56-10sa-5.0c 8p3 8s1 automotive ( ? 40 c to 125 c) at93c56-10pa-2.7c at93c56-10sa-2.7c 8p3 8s1 automotive ( ? 40 c to 125 c) package type 8p3 8-lead, 0.300" wide, plastic dual inline package (pdip) 8s1 8-lead, 0.150" wide, plastic gull wing small outline (jedec soic) options ? 5.0 standard operation (4.5v to 5.5v) ? 2.7 low voltage (2.7v to 5.5v)
12 at93c46/56/66 3264e?seepr?10/04 note: 1. this device is not recommended for new designs. please refer to at93c66a. at93c66 (1) ordering information ordering code package operation range at93c66-10pa-5.0c at93c66-10sa-5.0c 8p3 8s1 automotive ( ? 40 c to 125 c) at93c66-10pa-2.7c at93c66-10sa-2.7c 8p3 8s1 automotive ( ? 40 c to 125 c) package type 8p3 8-lead, 0.300" wide, plastic dual inline package (pdip) 8s1 8-lead, 0.150" wide, plastic gull wing small outline (jedec soic) options ? 5.0 standard operation (4.5v to 5.5v) ? 2.7 low voltage (2.7v to 5.5v)
13 at93c46/56/66 3264e?seepr?10/04 packaging information 8p3 ? pdip 2 3 25 orch a rd p a rkw a y sa n jo s e, ca 951 3 1 title drawing no. r rev. 8 p 3 , 8 -le a d, 0. 3 00" wide body, pl as tic d ua l in-line p a ck a ge (pdip) 01/09/02 8 p 3 b note s : 1. thi s dr a wing i s for gener a l inform a tion only; refer to jedec dr a wing m s -001, v a ri a tion ba, for a ddition a l inform a tion. 2. dimen s ion s a a nd l a re me asu red with the p a ck a ge s e a ted in jedec s e a ting pl a ne g au ge g s - 3 . 3 . d, d1 a nd e1 dimen s ion s do not incl u de mold fl as h or protr us ion s . mold fl as h or protr us ion s s h a ll not exceed 0.010 inch. 4. e a nd ea me asu red with the le a d s con s tr a ined to b e perpendic u l a r to d a t u m. 5. pointed or ro u nded le a d tip s a re preferred to e as e in s ertion. 6. b 2 a nd b3 m a xim u m dimen s ion s do not incl u de d a m ba r protr us ion s . d a m ba r protr us ion s s h a ll not exceed 0.010 (0.25 mm). common dimen s ion s (unit of me asu re = inche s ) s ymbol min nom max note d d1 e e1 e l b 2 b a2 a 1 n ea c b3 4 plc s a ? ? 0.210 2 a2 0.115 0.1 3 0 0.195 b 0.014 0.01 8 0.022 5 b 2 0.045 0.060 0.070 6 b3 0.0 3 0 0.0 3 9 0.045 6 c 0.00 8 0.010 0.014 d 0. 3 55 0. 3 65 0.400 3 d1 0.005 ? ? 3 e 0. 3 00 0. 3 10 0. 3 25 4 e1 0.240 0.250 0.2 8 0 3 e 0.100 b s c ea 0. 3 00 b s c 4 l 0.115 0.1 3 0 0.150 2 top view s ide view end view
14 at93c46/56/66 3264e?seepr?10/04 8s1 ? jedec soic 1150 e. cheyenne mtn. blvd. colorado springs, co 80906 title drawing no. r rev. note: 10/7/03 8s1 , 8-lead (0.150" wide body), plastic gull wing small outline (jedec soic) 8s1 b common dimensions (unit of measure = mm) symbol min nom max note a1 0.10 ? 0.25 these drawings are for general information only. refer to jedec drawing ms-012, variation aa for proper dimensions, tolerances, datums, etc. a 1.35 ? 1.75 b 0.31 ? 0.51 c 0.17 ? 0.25 d 4.80 ? 5.00 e1 3.81 ? 3.99 e 5.79 ? 6.20 e 1.27 bsc l 0.40 ? 1.27 ? 0? ? 8? ? top view end view side view e b d a a1 n e 1 c e1 l
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